Patent Number: 6,528,886

Title: Intermetal dielectric layer for integrated circuits

Abstract: An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

Inventors: Liu; Huang (Singapore, SG), Sudijono; John (Singapore, SG), Tan; Juan Boon (Singapore, SG), Goh; Edwin (Singapore, SG), Cuthbertson; Alan (Singapore, SG), Ang; Arthur (Singapore, SG), Chen; Feng (Singapore, SG), Li; Qiong (Singapore, SG), Chew; Peter (Singapore, SG)

Assignee: Chartered Semiconductor Manufacturing LTD

International Classification: H01L 21/768 (20060101); H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/316 (20060101); H01L 023/48 (); H01L 023/52 (); H01L 029/40 ()

Expiration Date: 03/04/2020