Patent Number: 6,528,888

Title: Integrated circuit and method

Abstract: An integrated circuit. The circuit includes a memory cell array including wordlines 201 formed on a substrate and bitlines 200 and capacitors 203 formed over the wordlines. The bitlines have a first thickness and pitch. The circuit also includes circuits peripheral to the array including transistors formed in the substrate and conductors 202 over the transistors. The conductors have a second thickness and pitch. The circuit is further characterized in that the bitlines and conductors are formed in a common conductive layer. In further embodiments, the first thickness and pitch are smaller than the second thickness and pitch.

Inventors: Cho; Chih-Chen (Richardson, TX), McKee; Jeffrey A. (Grapevine, TX), McKee; William R. (Plano, TX), Asano; Isamu (Iruma, JP), Tsu; Robert Y. (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/3205 (20060101); H01L 21/8242 (20060101); H01L 27/108 (20060101); H01L 023/48 ()

Expiration Date: 03/04/2020