Patent Number: 6,528,896

Title: Scalable two transistor memory device

Abstract: A Scalable Two-Transistor Memory (STTM) cell array having a 4F.sup.2 unitcell area, where F is the minimum feature size. The data lines and the bitlines alternate and are adjacent to each other along the Y-axis direction,and the word lines are laid out along the X-axis direction. Each STTM cellconsists of a floating gate MOS sensing transistor at the surface of asemiconductor substrate, with a vertical double sidewall gate multipletunnel junction barrier programming MOS transistor on top of the sensingtransistor. A data line connects all source regions of the programmingtransistors and a bit line connects all the source/drain regions of thesensing transistors in a column direction. A word line connects all doublesidewall gate regions of programming transistors in a row direction. Thisinvention also deals with a column addressing circuit as well as thedriving method for the circuit.

Inventors: Song; Seungheon (Sungnam, KR), Kim; Woosik (Suwon, KR), Kang; Hokyu (Sungnam, KR)


International Classification: G11C 16/04 (20060101); H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 27/115 (20060101); H01L 21/8247 (20060101); H01L 29/788 (20060101); H01L 027/11 ()

Expiration Date: 03/02015