Patent Number: 6,528,897

Title: Semiconductor memory device

Abstract: A semiconductor memory device may be formed from a pair of transfer MOStransistors 1, 2 controlled by a word line 11 and a pair of data retainingflip-flop circuit formed from serially connected load elements 5, 6 anddrive MOS transistors 3, 4. In the semiconductor memory device, thetransfer MOS transistors 1, 2 have a threshold voltage greater than athreshold voltage of the drive MOS transistors 3, 4. The memory device maydisplay an improved .beta. ratio, and reduce the size of the drive MOStransistors to thereby reduce the cell area.

Inventors: Kuwazawa; Kazunobu (Sakata, JP)

Assignee:

International Classification: G11C 11/412 (20060101); H01L 27/11 (20060101); H01L 027/10 (); H01L 029/73 (); H01L 029/76 (); H01L 029/94 (); H01L 031/062 (); H01L 031/113 (); H01L 031/119 (); H01L 027/11 ()

Expiration Date: 03/02015