Patent Number: 6,529,022

Title: Wafer testing interposer for a conventional package

Abstract: The present invention provides a wafer interposer for electrical testingand assembly into a conventional package. The present invention providesan interposer comprising a support having an upper and a lower surface.One or more solder bumps are on the lower surface. One or more firstelectrical terminals are on the upper surface, substantially correspondingto the position of the solder bumps, and forming a pattern. One or morefirst electrical pathways pass through the surface of the support andconnect the solder bumps to the first electrical terminals. One or moresecond electrical terminals are on the upper surface of the support. Thesecond electrical terminals are larger in size and pitch than the firstelectrical terminals, and they are located within the pattern formed bythe first electrical terminals. One or more second electrical pathwaysconnect the first electrical pathways to the second electrical pathway.

Inventors: Pierce; John L. (Dallas, TX)


International Classification: G01R 1/04 (20060101); G01R 1/02 (20060101); G01R 031/02 (); H05K 007/06 (); H05K 001/00 ()

Expiration Date: 03/02015