Patent Number: 6,529,035

Title: Arrangement for improving the ESD protection in a CMOS buffer

Abstract: An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width W.sub.N which is larger than the finger width W.sub.P of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.

Inventors: Schroeder; Hans-Ulrich (Quickborn, DE), Reiner; Joachim Christian (Thalwil, CH)

Assignee: Koninklijke Philips Electronics N.V.

International Classification: H01L 27/02 (20060101); H03K 019/017 ()

Expiration Date: 03/04/2011