Patent Number: 6,529,045

Title: NMOS precharge domino logic

Abstract: A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, with the gate of the clock transistor coupled to receive an inverse clock signal. A first inverter and a second inverter are connected in series such that the input of the first inverter is connected to the output of the second inverter. The input of the second inverter is connected to the dynamic output node. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection.

Inventors: Ye; Yibin (Portland, OR), Spotten; Reed D. (Hillsboro, OR), De; Vivek K. (Beaverton, OR)

Assignee: Intel Corporation

International Classification: H03K 19/096 (20060101); H03K 19/017 (20060101); H03K 19/01 (20060101); H03K 019/096 ()

Expiration Date: 03/04/2011