Patent Number: 6,529,049

Title: Pre-charged sample and hold

Abstract: A buffered sample-and-hold circuit includes two sampling capacitors for each analog voltage to be sampled. The two sampling capacitors are initially charged simultaneously to the analog voltage to be sampled. One of such sampling capacitors is thereafter temporarily coupled to the input terminal of a unity gain amplifier to pre-charge such input terminal, and any associated parasitic capacitance, to a voltage very near the actual sampled analog voltage. Following such pre-charge operation, that sampling capacitor is de-coupled from the input terminal of the amplifier; the other sampling capacitor is then coupled to the input terminal of the amplifier for establishing the actual sampled voltage at the input terminal of the amplifier.

Inventors: Erhart; Richard Alexander (Chandler, AZ), Ciccone; Thomas W. (Tempe, AZ)

Assignee: National Semiconductor Corporation

International Classification: H03K 5/00 (20060101); H03K 005/00 ()

Expiration Date: 03/04/2020