Patent Number: 6,529,051

Title: Frequency multiplier without spurious oscillation

Abstract: A damping resistance 20 is connected between the drain D of an FET 10 and a first end T3 of an output transmission line 13, and a damping resistance 21 is connected between the drain D of an FET 11 and the first end T3. The source of the FET 10 and the gate of the FET 11 are connected to a ground plane on the back surface of a substrate through a via which has a parasitic inductance when a multiplied frequency exceeds 20 GHz. The gate of the FET 10 and the source of the FET 11 receive microwaves of the same frequency and phase through an input transmission line 12.

Inventors: Tokumitsu; Tsuneo (Yamanashi-ken, JP), Baba; Osamu (Yamanashi-ken, JP)

Assignee: Fujitsu Quantum Devices Limited

International Classification: H03B 19/00 (20060101); H03B 019/00 ()

Expiration Date: 03/04/2020