Patent Number: 6,529,058

Title: Apparatus and method for obtaining stable delays for clock signals

Abstract: A circuit and method for obtaining a stable delay for a clock signal comprises a current source to generate a constant current having a first value; first and second current over capacitance (I/C) stages coupled to the current source and between a supply voltage and ground; and a capacitor, having a second value and coupled to a node formed by an output of the first I/C stage and an input of the second I/C stage. Application of a clock signal to an input of the first I/C stage produces an output at a logic gate coupled to an output of the second I/C stage. The output has a stable delay based on the first and second values. Additionally, the first and second values (i.e., the value of the current or capacitance) can be changed to achieve a desired amount of the delay applied to the input clock signal.

Inventors: Gupta; Sandeep Kumar (Mountain View, CA)

Assignee: Broadcom Corporation

International Classification: H03K 5/13 (20060101); H03K 5/00 (20060101); H03H 011/26 ()

Expiration Date: 03/04/2020