Patent Number: 6,612,159

Title: Overlay registration error measurement made simultaneously for more than two semiconductor wafer layers

Abstract: An improved target and a technique for using it to measure registration relative to each other of more than two layers of a semiconductor wafer. At least first, second and third layers are formed to overlay each other. A first pattern is provided in a designated location of the first layer. A second pattern is provided in a designated location of the second layer, such second pattern having a given shape and a given size, and having at least one discontinuity formed therein at a predetermined location. A third pattern is provided in a designated location of the third layer, such third pattern having the given shape and the given size of the second pattern, and having at least one discontinuity formed therein at a predetermined location, wherein a portion of each one of the second and third patterns fits within the at least one discontinuity in the other when the second and third layers are in registration with each other.

Inventors: Knutrud; Paul C. (Marlborough, MA)

Assignee: Schlumberger Technologies, Inc.

International Classification: G03F 7/20 (20060101); H01L 23/544 (20060101); G01B 005/28 ()

Expiration Date: 09/02/2020