Patent Number: 6,617,211

Title: Method for forming a memory integrated circuit

Abstract: A process for fabricating a crown-cell capacitor in a memory integrated circuit. The process includes the step of forming a transistor having a contact region 353 at a surface of a semiconductor substrate 300. The transistor, with the exception of the contact region, is covered with a first material 362, 366 and the first material and the contact region are then covered with a layer of a second material 370. The portion of the second layer covering the contact region is removed to expose the contact region so that the removal of the portions of the second layer forms a cavity characterized by a bottom formed of the first material and sides formed of the second material. Further steps in the process include forming a first conductive layer 372 in the cavity to contact the contact region and conform to the bottom and sides, forming a dielectric layer 376 over the first conductive layer, and forming a second conductive layer 378 over the dielectric layer.

Inventors: Niuya; Takayuki (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/8242 (20060101); H01L 21/70 (20060101); H01L 21/60 (20060101); H01L 21/02 (20060101); H01L 021/824 (); H01L 021/20 (); H01L 021/479 (); H01L 021/44 ()

Expiration Date: 09/09/2020