Patent Number: 6,617,216

Title: Quasi-damascene gate, self-aligned source/drain methods for fabricatingdevices

Abstract: Methods for use in fabricating integrated circuit structures. Oneembodiment of the present invention is a quasi-damascene gate,self-aligned source/drain method for forming a device on a substrate thatincludes steps of: (a) forming a gate dielectric layer over the substrate;(b) forming a first gate electrode layer over the gate dielectric layer;(c) forming a contact etch stop layer over the first gate electrode layer;(d) forming a self-aligning layer over the contact etch stop layer; and(e) forming and patterning a mask over the self-aligning layer.

Inventors: Hu; Hung-Kwei (Saratoga, CA)


International Classification: H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 021/336 ()

Expiration Date: 09/02015