Patent Number: 6,670,689

Title: Semiconductor device having shallow trench isolation structure

Abstract: A semiconductor device having a shallow trench isolation (STI) structure, which reduces leakage current between adjacent P-FETs, and a manufacturing method thereof. The device comprises a semiconductor substrate having first and second trenches, the first trench being formed in a cell area; a first sidewall oxide layer formed on inner surfaces of the first and second trenches; a second sidewall oxide layer formed on a surface of the first sidewall oxide layer in the second trench; a first relief liner formed on the first sidewall oxide layer in the first trench; a second relief liner formed on the first relief liner in the first trench, and also formed on the second sidewall oxide layer in the second trench; and a dielectric material formed within the first and second trenches.

Inventors: Oh; Yong-Chul (Kyungki-do, KR), Roh; Jun-Yong (Incheon, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/762 (20060101); H01L 21/70 (20060101); H01L 029/00 (); H01L 021/76 ()

Expiration Date: 12/30/2020