Patent Number: 6,670,690

Title: Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages

Abstract: A method and structure for forming a modified field oxide region having increased field oxide threshold voltages (V.sub.th) and/or reduced leakage currents between adjacent device areas is achieved. The method involves forming a field oxide using the conventional local oxidation of silicon (LOCOS) using a patterned silicon nitride layer as a barrier to oxidation. After forming the LOCOS field oxide by thermal oxidation and removing the silicon nitride, a conformal insulating layer composed of silicon oxide is deposited and anisotropically etched back to form sidewall insulating portions over the bird's beak on the edge of the LOCOS field oxide, thereby forming a new modified field oxide. P-channel implants are formed in the device areas. Then a second implant is used to implant through the modified field oxide to provide channel-stop regions with modified profiles that increase the field oxide V.sub.th and/or reduce leakage current between device areas. This improved field oxide/channel-stop structure is particularly useful for reducing the leakage current on DRAM cells thereby increasing the refresh cycle times.

Inventors: Yoo; Chue-San (Hsin-Chu, TW), Shih; Cheng-Yeh (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: H01L 21/02 (20060101); H01L 21/70 (20060101); H01L 21/762 (20060101); H01L 21/32 (20060101); H01L 021/76 ()

Expiration Date: 12/30/2020