Patent Number: 6,670,714

Title: Semiconductor integrated circuit device having multilevel interconnection

Abstract: One via contact through which upper and lower interconnections of a multilevel interconnection are connected to each other is provided when the width or volume of the lower interconnection is not larger than a given value. A plurality of via contacts are arranged at regular intervals, each of which is not larger than a given value, in an effective diffusion region of voids included in the lower interconnection, when the width or volume of the lower interconnection exceeds a given value.

Inventors: Miyamoto; Koji (Yokohama, JP), Yoshida; Kenji (Kawasaki, JP), Kaneko; Hisashi (Fujisawa, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: H01L 23/52 (20060101); H01L 23/532 (20060101); H01L 23/522 (20060101); H01L 023/48 (); H01L 023/40 (); H01L 023/50 ()

Expiration Date: 12/30/2020