Patent Number: 6,670,835

Title: Delay locked loop for controlling phase increase or decrease and phasecontrol method thereof

Abstract: A delay locked loop which is capable of adjusting the number of delaydevices in a delay line and controlling a phase increase or decrease moreprecisely than the adjustment by the number of delay devices and a phasecontrol method thereof are provided. The delay locked loop includes aphase detector, a delay line, and a delay time adjuster. The phasedetector compares the phase of a reference clock signal with the phase ofa feedback clock signal and outputs the phase difference between thereference clock signal and the feedback clock signal as an error controlsignal. The delay line includes a plurality of first delay devices havinga fixed delay time and connected in series. The number of first delaydevices connected in series is adjusted in response to a shift signal. Thedelay line receives an input clock signal and outputs an output clocksignal. The delay time adjuster controls a delay time in response to thereference clock signal and the error control signal generated from thephase detector, generates the input clock signal and adjusts the number offirst delay devices.

Inventors: Yoo; Chang-sik (Suwon, KR)

Assignee:

International Classification: H03L 7/08 (20060101); H03L 7/081 (20060101); H03L 007/06 ()

Expiration Date: 12/32016