Patent Number: 6,674,313

Title: Output buffer circuit

Abstract: An output buffer circuit having a function of accomplishing pre-emphasis, and transmitting a logic signal to a transmission line acting as a distributed parameter circuit, includes (a) a first buffer which receives a first logic signal defining a logical value of a logic signal to be transmitted to the transmission line, and drives the transmission line, and (b) a second buffer which receives a second logic signal having a predetermined logical relation with the first logic signal, and cooperates with the first buffer to drive the transmission line. The second buffer has an output impedance higher than an output impedance of the first buffer as long as attenuation in a signal in the transmission line is improved.

Inventors: Kurisu; Masakazu (Tokyo, JP), Nedachi; Takaaki (Tokyo, JP)

Assignee: NEC Electronics Corporation

International Classification: H04L 25/02 (20060101); H03B 001/00 ()

Expiration Date: 01/06/2021