Patent Number: 6,674,317

Title: Output stage of a charge pump circuit providing relatively stable output voltage without voltage degradation

Abstract: An output stage and method for a charge pump circuit which substantially reduces the degradation of the output voltage. A first NMOS transistor has its source connected to an input node and its drain connected to a second node. A second NMOS transistor has its source connected to the input node, its gate connected to the drain of the first NMOS transistor, and its drain connected to the gate of the first NMOS transistor. A capacitor is connected between a second clock signal and the drain of the second NMOS transistor. Another capacitor is connected between a first clock signal and an intermediate node. The key part of the invention is a diode pair connected anode of one to the cathode of the other and inserted between the intermediate node and the drain of the first NMOS transistor. This has the effect of changing a parallel combination of capacitors to a series combination of capacitors, thereby reducing the degradation of the output voltage and providing a stable voltage to the gate of an NMOS transistor switch in the output of the circuit.

Inventors: Chou; Shao Yu (Tao-yuan, TW)

Assignee: Taiwan Semiconductor Manufacturing Company

International Classification: G06F 7/64 (20060101); G06F 7/60 (20060101); G06F 007/64 ()

Expiration Date: 01/06/2021