Patent Number: 6,683,380

Title: Integrated circuit with bonding layer over active circuitry

Abstract: An integrated circuit device (10) with a bonding surface (12) directly over its active circuitry, and a method of making such integrated circuits (FIGS. 2A-2E). To make the bonding surface (12), a wafer (20) is provided with vias (24) to its metallization layer (21) and then coated with a seed metal layer (25). A plating pattern (26) is formed on the wafer (20), exposing portions of the seed metal layer (25) and blocking the rest of the seed metal layer (25). These exposed portions are plated with successive metal layers (27, 28, 29), thereby forming a bonding surface (12) having a number of layered stacks (200) that fill the vias (24). The plating pattern and the nonplated portions of the seed metal layer (25) are then removed.

Inventors: Efland; Taylor R. (Richardson, TX), Abbott; Donald C. (Norton, MA), Bucksch; Walter (Freising, DE), Corsi; Marco (Allen, TX), Shen; Chi-Cheong (Richardson, TX), Erdeljac; John P. (Plano, TX), Hutter; Louis N. (Plano, TX), Mai; Quang X. (Sugarland, TX), Wagensohner; Konrad (Mauern, DE), Williams; Charles E. (Dallas, TX), Buschbom; Milton L. (Plano, TX)

Assignee: Texas Instruments Incorporated

International Classification: H01L 21/60 (20060101); H01L 21/02 (20060101); H01L 023/48 ()

Expiration Date: 01/27/2021