Patent Number: 6,683,382

Title: Semiconductor device having an interconnect layer with a plurality of layout regions having substantially uniform densities of active interconnects and dummy fills

Abstract: A semiconductor device with an interconnect layer having a plurality of layout regions of active interconnects and dummy fills for uniform planarization. In one embodiment, the device will have at least one interconnect layer with a plurality of layout regions overlying the semiconductor substrate. Each layout region will comprise an active interconnect feature region and a dummy fill feature region adjacent thereto for facilitating uniformity of planarization during manufacturing. Each dummy fill region in each layout region will have a different density with respect to other dummy fill regions in other layout regions, so that the combined density of the active interconnect feature region and the dummy fill feature region in a layout region will be substantially uniform with respect to a similar combined density in each of the other layout regions.

Inventors: Cwynar; Donald Thomas (Orlando, FL), Misra; Sudhanshu (Orlando, FL), Ouma; Dennis Okumu (Somerset, NJ), Saxena; Vivek (Orlando, FL), Sharpe; John Michael (Allentown, PA)

Assignee: Agere Systems Inc.

International Classification: H01L 23/52 (20060101); H01L 21/70 (20060101); H01L 21/768 (20060101); H01L 23/528 (20060101); H01L 027/10 (); G03F 009/00 ()

Expiration Date: 01/27/2021