Patent Number: 6,683,483

Title: Clock pulse width control circuit

Abstract: Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Inventors: Witte; Jeffrey Paul (Fort Collins, CO), Zhu; Quanhong (Fort Collins, CO), Josephson; Don D. (Fort Collins, CO)

Assignee: Hewlett-Packard Development Company, L.P.

International Classification: H03K 3/00 (20060101); H03K 3/017 (20060101); H03K 003/017 ()

Expiration Date: 01/27/2021