Patent Number: 6,683,506

Title: CMOS phase locked loop with voltage controlled oscillator having realignment to reference and method for the same

Abstract: A periodic controlled realignment of the ring oscillator VCO in a phase locked loop is used to effect phase correction in a CMOS phase locked loop. A realignment to a buffered version of the reference signal is conducted periodically, at a time when an edge of the VCO waveform would ideally coincide with an edge in the reference signal. A preferred embodiment CMOS phase locked loop of the invention uses a ring oscillator voltage controlled oscillator. A divide by M circuit is driven by an output of the voltage controlled oscillator. A control voltage circuit accepts a reference signal and a signal from the divide by M circuit, and produces a control voltage proportional to a phase difference between the output of the voltage controlled oscillator and the reference signal to control the voltage controlled oscillator. A realignment circuit responsive to the reference signal provides a realignment signal into the voltage controlled oscillator when an edge in the waveform of the voltage controlled oscillator ideally coincides with an edge of the reference signal.

Inventors: Ye; Sheng (La Jolla, CA), Galton; Ian (Del Mar, CA)

Assignee: The Regents of the University of California

International Classification: H03L 7/099 (20060101); H03L 7/08 (20060101); H03L 7/16 (20060101); H03L 7/18 (20060101); H03L 7/083 (20060101); H03B 027/00 ()

Expiration Date: 01/27/2021