Patent Number: 6,762,098

Title: Trench DMOS transistor with embedded trench schottky rectifier

Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions. The integrated circuit comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower doping level than the substrate; (c) a plurality of body regions of a second conductivity type within the epitaxial layer in the transistor regions; (d) a plurality of trenches within the epitaxial layer in both the transistor regions and the rectifier regions; (e) a first insulating layer that lines the trenches; (f) a polysilicon conductor within the trenches and overlying the first insulating layer; (g) a plurality of source regions of the first conductivity type within the body regions at a location adjacent to the trenches; (h) a second insulating layer over the doped polysilicon layer in the transistor regions; and (i) an electrode layer over both the transistor regions and the rectifier regions.

Inventors: Hshieh; Fwu-Iuan (Saratoga, CA), Tsui; Yan Man (Union City, CA), So; Koon Chong (Fremont, CA)

Assignee: General Semiconductor, Inc.

International Classification: H01L 29/66 (20060101); H01L 21/02 (20060101); H01L 21/336 (20060101); H01L 27/06 (20060101); H01L 29/78 (20060101); H01L 021/336 ()

Expiration Date: 07/13/2021