Patent Number: 6,762,111

Title: Method of manufacturing a semiconductor device

Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

Inventors: Fukuda; Hiroshi (Kodaira, JP)

Assignee: Renesas Technology Corporation

International Classification: H01L 23/544 (20060101); H01I 021/76 ()

Expiration Date: 07/12016