Patent Number: 6,762,126

Title: Method of forming an interlayer dielectric film

Abstract: In a method for forming an interlayer dielectric film, an insulating film is deposited on a semiconductor substrate that has a metal wiring pattern. The insulating film is polished by CMP until exposing an upper portion of the wiring pattern. A spin on glass composition, which includes polysilazane, is coated over the polished insulating material and exposed portions of the wiring pattern to form a film. The film is then pre-baked in a temperature range of 50 to C., and then hard-baked in a temperature range of 300 to C. After the hard-baking, the film is then heat-treated in an oxidation atmosphere. With the hard-baking, gasses of the coating of film may be removed so that the amount of gas generated during a subsequent anneal or heat-treating process may be reduced. Accordingly, particle contaminants may be reduced by such process in addition to providing a means for reduced risk of crack formation.

Inventors: Cho; Young-Joo (Gyeonggi-do, KR), Hong; Eun-Kee (Gyeonggi-do, KR), Lee; Ju-Bum (Gyeonggi-do, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 21/02 (20060101); H01L 21/312 (20060101); H01L 021/311 ()

Expiration Date: 07/13/2021