Patent Number: 6,762,433

Title: Semiconductor product wafer having vertically and horizontally arranged patterned areas including a limited number of test element group regions

Abstract: A plurality of patterned areas is arranged vertically and horizontally with fixed pitches on a surface of a semiconductor product wafer. The patterned areas include a plurality of first patterned areas and at least one second patterned area. The first patterned area includes a device region, and the second patterned area includes a portion of the device region and a Test Element Group (TEG) region.

Inventors: Yamaguchi; Takahisa (Mihama-ku, JP)

Assignee: Kawasaki Microelectronics, Inc.

International Classification: G03F 7/20 (20060101); H01L 23/544 (20060101); H01L 023/544 ()

Expiration Date: 07/13/2021