Patent Number: 6,762,464

Title: N-p butting connections on SOI substrates

Abstract: An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

Inventors: Webb; Clair (Aloha, OR), Bohr; Mark (Aloha, OR)

Assignee: Intel Corporation

International Classification: H01L 21/70 (20060101); H01L 27/12 (20060101); H01L 27/11 (20060101); H01L 21/84 (20060101); H01L 21/8244 (20060101); H01L 027/01 ()

Expiration Date: 07/13/2021