Patent Number: 6,763,385

Title: Coordination of multiple processor bus tracings for enabling study of multiprocessor multi-bus computer systems

Abstract: In particular, a system and method for receiving high speed processor bus traces for study of computer system capacity and operation uses a collection of coordinated collector system to collect trace data for a plurality of processor busses operating at the same time in a multiprocessor computer system under test. Pipelined bus communications on the processor bus are aligned, in one mode, and in another, multiple instructions on split domain busses are aligned. In both cases a time stamp is obtained to match each processor word to a time of occurrence to facilitate study of the trace data. All time stamps from the various busses being studied and from which trace data is being collected have the same values at any given time so that the data collected from each bus can be coordinated with data from the other busses of the plurality by the reading of the time stamps.

Inventors: Orfali; Marwan A. (Woodbury, MN)

Assignee: Unisys Corporation

International Classification: G06F 11/34 (20060101); G06F 013/00 (); G06F 011/34 ()

Expiration Date: 07/13/2021