Patent Number: 6,763,433

Title: High performance cache intervention mechanism for symmetric multiprocessor systems

Abstract: Upon snooping an operation in which an intervention is permitted or required, an intervening cache may elect to source only that portion of a requested cache line which is actually required, rather than the entire cache line. For example, if the intervening cache determines that the requesting cache would likely be required to invalidate the cache line soon after receipt, less than the full cache line may be sourced to the requesting cache. The requesting cache will not cache less than a full cache line, but may forward the received data to the processor supported by the requesting cache. Data bus bandwidth utilization may therefore be reduced. Additionally, the need to subsequently invalidate the cache line within the requesting cache is avoided, together with the possibility that the requesting cache will retry an operation requiring invalidation of the cache line.

Inventors: Arimilli; Ravi K. (Austin, TX), Dodson; John Steven (Pflugerville, TX), Fields, Jr.; James Stephen (Austin, TX), Guthrie; Guy Lynn (Austin, TX)

Assignee: International Business Machines Corporation

International Classification: G06F 12/08 (20060101); G06F 012/08 ()

Expiration Date: 07/13/2021