Patent Number: 6,763,435

Title: Super-coherent multiprocessor system bus protocols

Abstract: A method for improving performance of a multiprocessor data processing system comprising snooping a request for data held within a shared cache line on a system bus of the data processing system whose cache contains an updated copy of the shared cache line, and responsive to a snoop of the request by the second processor, issuing a first response on the system bus indicating to the requesting processor that the requesting processor may utilize data currently stored within the shared cache line of a cache of the requesting processor. When the request is snooped by the second processor and the second processor decides to release a lock on the cache line to the requesting processor, the second processor issues a second response on the system bus indicating that the first processor should utilize new/coherent data and then the second processor releases the lock to the first processor.

Inventors: Arimilli; Ravi Kumar (Austin, TX), Guthrie; Guy Lynn (Austin, TX), Starke; William J. (Round Rock, TX), Williams; Derek Edward (Austin, TX)

Assignee: International Buisness Machines Corporation

International Classification: G06F 13/00 (20060101); G06F 13/14 (20060101); G06F 013/14 ()

Expiration Date: 07/13/2021