Patent Number: 6,763,489

Title: Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description

Abstract: A method for at-speed scan testing of circuits having scannable memory elements which source multi-cycle paths having propagation delays that are longer than the period of a system clock used during normal operation comprises loading a test stimulus into the scannable memory elements; performing a capture operation, including configuring in capture mode throughout the capture operation, non-source memory elements and multi-cycle path source memory elements which have a predetermined maximum capture clock rate which is the same as or higher than the clock rate of the capture clock; and configuring in a hold mode during all but the last cycle of the capture operation and in capture mode for the last cycle, source memory elements which have a predetermined maximum capture clock rate which is lower than the clock rate of the capture clock; applying at least two clock cycles of the capture clock; and unloading test response data captured by said scannable memory elements.

Inventors: Nadeau-Dostie; Benoit (Aylmer, CA), Cote; Jean-Fran.cedilla.ois (Chelsea, CA)

Assignee: LogicVision, Inc.

International Classification: G01R 31/3185 (20060101); G01R 31/28 (20060101); G01R 031/28 ()

Expiration Date: 07/13/2021