Patent Number: 6,763,503

Title: Accurate wire load model

Abstract: A method for creating a wire load model using specific interconnect configuration information is provided. Further, a program that creates a wire load model by curve-interconnect fitting parasitic information and interconnect configuration information is provided. Further, a computer system capable of creating an accurate wire load model using parasitic information specific to particular metal layers is provided.

Inventors: Yang; Xiao-Dong (Sunnyvale, CA), Vidhani; Devendra (Sunnyvale, CA), Konstadinidis; Georgios (Sunnyvale, CA)

Assignee: Sun Microsystems, Inc.

International Classification: G06F 17/50 (20060101); G06F 9/45 (20060101); G06F 017/50 (); G06F 009/45 ()

Expiration Date: 07/13/2021