Patent Number: 6,763,504

Title: Method for reducing RC parasitics in interconnect networks of an integrated circuit

Abstract: A method for further reducing RC parasitics in an interconnect network following internal node elimination is described. A resistor is initially selected as a candidate for shorting, and it is established whether the accumulated delay error at either end of the resistor is less than a predetermined threshold. This threshold must be a fraction of the time-constant threshold selected by internal node elimination techniques in order to limit the growth of the accumulated delay errors. An important aspect of the invention is the simplicity of the formula used to change the downstream resistor values, namely, the product of the value of the resistor shorted and the ratio of the cumulative downstream capacitances of the two ends of the resistor whose value is being changed. This particular choice of updating the downstream resistor values minimizes the absolute-value of the delay errors at every node due to shorting of the selected resistor. It also preserves the delays at all nodes in the interconnect network apart from the two ends of the resistor selected for shorting.

Inventors: Rao; Vasant B. (Fishkill, NY), Ledalla; Ravichander (Beacon, NY), Soreff; Jeffrey P. (Poughkeepsie, NY), Yang; Fred L. (Fremont, CA)

Assignee: International Business Machines Corporation

International Classification: G06F 17/50 (20060101); G06F 017/50 ()

Expiration Date: 07/12016