Patent Number: 6,763,511

Title: Semiconductor integrated circuit having macro cells and designing method of the same

Abstract: The present invention enables to design a semiconductor integrated circuit with a small chip area and a small number of wiring layers at a low cost for a short time. In the present design method of the semiconductor integrated circuit, a first wiring group (a horizontal power wiring and horizontal ground wirings) and a second wiring group (a horizontal power wiring and horizontal ground wirings), which are opposite to each other, are arranged at the outside of a macro outer frame, a third wiring group (a vertical power wiring and a vertical ground wiring) is arranged to correspond to a power terminal and a ground terminal on a macro cell, and these first and second wiring groups are connected to the power terminal and the ground terminal by the third wiring group.

Inventors: Banno; Akihiro (Tokyo, JP), Ooshige; Shinichirou (Tokyo, JP), Shintani; Masaru (Kanagawa, JP), Matsui; Masaru (Kanagawa, JP)

Assignee: NEC Electronics Corporation

International Classification: G06F 17/50 (20060101); H01L 27/118 (20060101); H01L 27/02 (20060101); G06F 017/50 ()

Expiration Date: 07/12016