Patent Number: 6,794,704

Title: Method for enhancing electrode surface area in DRAM cell capacitors

Abstract: Lower electrodes of capacitors composed of a texturizing underlayer and a conductive material overlayer are provided. The lower electrodes have an upper roughened surface. In one embodiment, the texturizing layer is composed of porous or relief nanostructures comprising a polymeric material, for example, silicon oxycarbide. In another embodiment, the texturizing underlayer is in the form of surface dislocations composed of annealed first and second conductive metal layers, and the conductive metal overlayer is agglomerated onto the surface dislocations as nanostructures in the form of island clusters.

Inventors: Yates; Donald L. (Boise, ID), Mercaldi; Garry A. (Meridian, ID), Hofmann; James J. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 21/70 (20060101); H01L 21/02 (20060101); H01L 21/8242 (20060101); H01L 027/108 (); H01L 029/76 (); H01L 029/94 (); H01L 031/119 ()

Expiration Date: 09/22016