Patent Number: 6,794,741

Title: Three-dimensional stacked semiconductor package with pillars in pillar cavities

Abstract: A three-dimensional stacked semiconductor package includes first and second semiconductor chip assemblies and a conductive bond. The first semiconductor chip assembly includes a first semiconductor chip and a first conductive trace with a first routing line and a first pillar. The second semiconductor chip assembly includes a second semiconductor chip and a second conductive trace with a second routing line and a second pillar. The chips are aligned with one another, the pillars are disposed outside the peripheries of the chips and aligned with one another, and the first pillar extends into a cavity in the second pillar. The conductive bond is within the cavity and contacts and electrically connects the pillars.

Inventors: Lin; Charles W. C. (Singapore, SG), Chiang; Cheng-Lien (Taipei, TW), Sigmond; David M. (Superior, CO)

Assignee: Bridge Semiconductor Corporation

International Classification: H01L 25/065 (20060101); H01L 023/52 (); H01L 023/34 (); H01L 023/44 ()

Expiration Date: 09/21/2021