Patent Number: 6,794,751

Title: Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies

Abstract: Multi-purpose planarizing/back-grind/pre-under-fill arrangements for bumped wafers and dies, in which a planarizing coating provides improved and continued surface protection to the circuit surface of a wafer or die throughout back-grinding and subsequent mounting operations, and provides improved stiffening/strengthening of the wafer and die throughout back-grinding and subsequent mounting operations.

Inventors: Kumamoto; Takashi (Tsukuba, JP)

Assignee: Intel Corporation

International Classification: H01L 21/56 (20060101); H01L 21/68 (20060101); H01L 21/67 (20060101); H01L 21/02 (20060101); H01L 023/48 (); H01L 021/00 ()

Expiration Date: 09/22016