Patent Number: 6,794,898

Title: Scan flip-flop circuit, scan flip-flop circuit array, and integrated circuit device

Abstract: A scan flip-flop circuit achieving higher operation speed, lower power consumption, and a simplified selector section, an array of the scan flip-flop circuits, and an integrated circuit device having therein the array are provided. In a scan flip-flop circuit, an output terminal is provided in addition to an output terminal. One of the output terminals is used for a logic circuit and the other output terminal is used for a scan flip-flop circuit of the next stage. At the output terminal for the scan flip-flop circuit 1 of the next stage, an output is fixed in a normal operation, thereby achieving higher operation speed in the normal operation and lower power consumption. A selector section can employ a relatively simple OR-AND-INVERTER structure.

Inventors: Komaki; Masaki (Kasugai, JP)

Assignee: Fujitsu Limited

International Classification: G01R 31/28 (20060101); G01R 31/3185 (20060101); H03K 019/173 ()

Expiration Date: 09/21/2021