Patent Number: 6,801,060

Title: Semiconductor integrated circuit

Abstract: In order to avoid any malfunction for a temporary change in power supply voltage and suppress decrease in internal power supply voltage when transition is effected from the stand-by mode to the active mode, the disclosed semiconductor integrated circuit is provided with a detecting circuit which prevents malfunction in a temporary change in the power supply voltage from occurring by changing a detection level according to when the power supply voltage is increased or decreased. Further, a decrease in the internal power supply voltage immediately after the transition from the stand-by mode to the active mode is suppressed by employing a PMOS down converter in the stand-by mode and an NMOS down converter in the active mode, and setting an internal power supply voltage of the PMOS down converter in the stand-by mode higher than in the active mode. A down converter is formed in a lower layer of an external power supply line and peripheral circuit blocks are arranged in a lower layer of internal power supply lines on both sides of the external power supply line symmetrically with respect thereto, whereby a power supply distance of the power supply voltage is minimized and controllability of the internal power supply voltage is improved.

Inventors: Ikehashi; Tamio (Kamakura, JP), Sugiura; Yoshihisa (Kamakura, JP), Imamiya; Kenichi (Kawasaki, JP), Takeuchi; Ken (Tokyo, JP), Iwata; Yoshihisa (Yokohama, JP)

Assignee: Kabushiki Kaisha Toshiba

International Classification: G05F 1/10 (20060101); G05F 1/46 (20060101); H03K 005/153 ()

Expiration Date: 10/02016