Patent Number: 6,801,181

Title: Level shifter for use in active matrix display apparatus

Abstract: Between a positive power supply 18 and a negative power supply 19, a p-channel transistor 11 and an n-channel transistor 14 are connected in series while a p-channel transistor 12 and an n-channel transistor 15 are also connected in series. An inverted input signal *Sig1 is input to the respective gates of the transistors 11 and 14, while an input signal Sig1 is input to the respective gates of the transistors 12 and 15. As a result, of a pair of the transistors connected in series, namely either the transistors 11 and 14 or the transistors 12 and 15, when one transistor turns ON, the other transistor turns OFF. Thus, generation of through currents is prevented.

Inventors: Matsumoto; Shoichiro (Ogaki, JP), Komiya; Naoaki (Ogaki, JP), Okuyama; Masahiro (Inazawa, JP), Hirosawa; Koji (Gifu, JP)

Assignee: Sanyo Electric Co., Ltd.

International Classification: G09G 3/36 (20060101); G09G 003/36 ()

Expiration Date: 10/05/2021