Patent Number: 6,803,640

Title: Capacitor

Abstract: The present invention relates to a WACC and a fabricating method thereof to prevent the occurrence of lifting between a polysilicon layer pattern and blocking metal layer of an upper electrode. In order to accomplish the object of the present invention, there is provided a capacitor having upper and lower electrodes and a dielectric layer therebetween, wherein the upper electrode has a polysilicon pattern constructed in a deposition structure of "first undoped polysilicon layer/doped polysilicon layer/second undoped polysilicon layer" to be connected with a first metal pattern at the top portion, and the lower electrode has first and second metal patterns to be connected with a p++ type silicon substrate at the bottom portion. The first metal pattern is preferably constructed in a deposition structure of "blocking metal layer/aluminum layer", where the blocking metal layer is preferably constructed in a "Ti/TiN" deposition structure. Accordingly, the capacitor is constructed to enable the blocking metal layer to be in contact with an undoped polysilicon layer, rather than a doped polysilicon layer as in conventional embodiments, to achieve an effect that the doffing level of the polysilicon layer is reduced as compared to the conventional configuration, thereby enhancing formation of the silicide layer between the polysilicon layer and the blocking metal layer to improve adhesion and prevent the occurrence of lifting.

Inventors: Lee; In-Jung (Seoul, KR), Shin; Heon-Joung (Yongin, KR)

Assignee: Samsung Electronics Co., Ltd.

International Classification: H01L 29/66 (20060101); H01L 27/08 (20060101); H01L 25/16 (20060101); H01L 29/94 (20060101); H01L 027/08 (); H01L 029/76 (); H01L 029/94 (); H01L 031/119 ()

Expiration Date: 10/12/2021