Patent Number: 6,806,515

Title: Layout of a decoder and the method thereof

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Inventors: Hsiao; Chuan-Cheng (Chiai, TW), Bu; Lin-Kai (Tainan, TW), Hung; Kun-Cheng (Hsinchu, TW), Chen; Chien-Pin (Yangkang, TW)

Assignee: Himax Technologies, Inc.

International Classification: G09G 3/36 (20060101); H01L 031/072 (); H01L 031/109 (); H01L 031/032 (); H01L 031/033 ()

Expiration Date: 10/19/2012