Patent Number: 6,841,824

Title: Flash memory cell and the method of making separate sidewall oxidation

Abstract: A process and product for making integrated circuits with dense logic and/or linear regions and dense memory regions is disclosed. On a common substrate, a dual hard mask process separately forms stacks of logic and/or linear transistors and EEPROM memory transistors. By using the process, the logic and/or linear and memory transistors are made with different sidewall insulating layers. The logic and/or linear transistors have relatively thin sidewall insulating layers sufficient to provide isolation from adjacent devices and conductors. The memory transistors have thicker sidewall insulating layer to prevent the charge stored in the memory device from adversely influencing the operation of the memory transistor.

Inventors: Shum; Danny (Wappingers Falls, NY)

Assignee: Infineon Technologies AG

International Classification: H01L 21/70 (20060101); H01L 21/8247 (20060101); H01L 27/105 (20060101); H01L 029/792 ()

Expiration Date: 01/11/2022