Patent Number: 6,841,852

Title: Integrated circuit package for semiconductor devices with improved electric resistance and inductance

Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a "L" shape, a "C" shape, a "J" shape, an "I" shape or any combination thereof.

Inventors: Luo; Leeshawn (Sunnyvale, CA), Bhalla; Anup (Sunnyvale, CA), Ho; Yueh-Se (Sunnyvale, CA), Lui; Sik K. (Sunnyvale, CA), Chang; Mike (Sunnyvale, CA)


International Classification: H01L 23/485 (20060101); H01L 21/02 (20060101); H01L 21/60 (20060101); H01L 23/50 (20060101); H01L 23/495 (20060101); H01L 23/48 (20060101); H01L 023/48 ()

Expiration Date: 01/11/2022