Patent Number: 6,885,045

Title: Layout structure of multiplexer cells

Abstract: A multiplexer cell layout structure is a layout structure of primitive cells where cell arrays composed of P-channel transistors and N-channel transistors are arranged in two upper and lower rows. And, a plurality of transistors of transfer gates are arranged on the upper side and lower side of the cell arrays, an output terminal of the plurality of arranged transistors is connected up and down by Metal wiring across between the upper and lower cell arrays. Thus, a multiplexer cell layout structure which increases wiring tracks of two-layer metal wiring for a one-chip layout held by a 4-input multiplexer inverter can be obtained.

Inventors: Hidaka; Itsuo (Kanagawa, JP)

Assignee: NEC Electronics Corporation

International Classification: H01L 21/70 (20060101); H01L 29/66 (20060101); H01L 21/822 (20060101); H01L 21/82 (20060101); H01L 27/10 (20060101); H01L 29/73 (20060101); H01L 27/118 (20060101); H01L 27/04 (20060101); H03K 17/687 (20060101); H01L 029/73 ()

Expiration Date: 4/26/02017