Patent Number: 6,885,062

Title: MOS transistor device with a locally maximum concentration region between the source region and the drain region

Abstract: In order to obtain an on resistance that is as low as possible, it is proposed, in the case of a MOS transistor device, to form the avalanche breakdown region in an end region of a trench structure. As an alternative or in addition, it is proposed to form a region of local maximum dopant concentration of a first conductivity type in the region between a source and a drain in proximity to the gate insulation in a manner remote from the gate electrode.

Inventors: Zundel; Markus (Taufkirchen, DE), Hirler; Franz (Isen, DE), Lantier; Roberta (Munchen, DE)

Assignee: Infineon Technologies AG

International Classification: H01L 29/78 (20060101); H01L 29/66 (20060101); H01L 29/40 (20060101); H01L 29/02 (20060101); H01L 29/08 (20060101); H01L 29/423 (20060101); H01L 29/10 (20060101); H01L 023/00 (); H01L 029/76 (); H01L 029/78 ()

Expiration Date: 04/26/2022