Patent Number: 6,885,063

Title: Semiconductor device having an SEB voltage suitable for use in space

Abstract: In a power MOSFET, on an N.sup.+ drain layer 21 as a substrate, a second N base layer 3 and a first N.sup.- base layer 22 are deposited in the order by epitaxial growth. In a surface portion of the layer 22, there are selectively formed a P base region 23, in a surface portion of which an N.sup.+ source region 24 is selectively formed. On a channel region in the P base region 23, a gate electrode 26 is formed with a gate insulator film 25 held between. A source electrode 27 and a drain electrode 28 are formed on the N.sup.+ source region 24 and on the back of the substrate, respectively. The layer 3 is made to have a thickness equal to or more than 1/4 of that of the first N.sup.- base layer 22, and an averaged impurity concentration between 1.times.10.sup.15 /cm.sup.3 and 3.times.10.sup.17 /cm.sup.3. The thickness can be alternatively given as equal to or more than 1/2 of a difference between the thickness x shown as x(.mu.m)=V.sub.SEB (V)/8 and that of the layer 22, where V.sub.SEB is an SEB(Single Event Burnout) voltage of the layer 3. This makes positive feed back hard to occur between latch-up of a parasitic npn transistor and dynamic avalanche near the substrate to enhance the SEB voltage, allowing the MOSFET to be applied to space use.

Inventors: Tagami; Saburo (Matsumoto, JP), Kobayashi; Takashi (Matsumoto, JP), Kirihata; Fumiaki (Matsumoto, JP), Kuboyama; Satoshi (Tokyo, JP)

Assignee: Fuji Electric Co., Ltd.

International Classification: H01L 29/66 (20060101); H01L 29/78 (20060101); H01L 29/02 (20060101); H01L 29/08 (20060101); H01L 029/78 ()

Expiration Date: 04/26/2022