Patent Number: 6,941,421

Title: Zero delay data cache effective address generation

Abstract: A method and system for accessing a specified cache line using previously decoded base address offset bits, stored with a register file, which eliminate the need to perform a full address decode in the cache access path, and to replace the address generation adder multiple level logic with only one level of rotator/multiplexer logic. The decoded base register offset bits enable the direct selection of the specified cache line, thus negating the need for the addition and the decoding of the base register offset bits at each access to the cache memory. Other cache lines are accessed by rotating the decoded base address offset bits, resulting in a selection of another cache word line.

Inventors: Luick; David Arnold (Rochester, MN)

Assignee: International Business Machines Corporation

International Classification: G06F 12/08 (20060101); G06F 12/02 (20060101); G06F 12/00 (20060101); G06F 012/00 ()

Expiration Date: 09/06/2022