Patent Number: 6,941,484

Title: Synthesis of a synchronization clock

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Inventors: To; Hing Y. (Folsom, CA), Salmon; Joseph H. (Placerville, CA), Williams; Michael W. (Citrus Heights, CA)

Assignee: Intel Corporation

International Classification: G06F 1/06 (20060101); G11C 7/10 (20060101); G11C 7/00 (20060101); G11C 7/22 (20060101); G06F 001/12 ()

Expiration Date: 09/06/2022